The use of wafers is a cost-effective way to concurrently fabricate many semiconductor chips. Each semiconductor chip may contain several million active and passive devices that make up the Integrated Circuit (IC) systems that are so prevalent in our world. The most familiar applications of IC systems are found in cellphones, camcorders, portable music players, televisions, and computers.
Once all the chips are fabricated and tested at the wafer level, the chips are separated from the wafer and assembled into final integrated circuit package systems. The assembly and package process takes Known Good Die (KGD), places them in a package, and interconnects the device bonding pads to the package leads. As customer demand improves chip performance, new requirements are placed on integrated circuit package. To meet this demand, the semiconductor industry had begun stacking individual chips and even packages one over the other in an effort to decrease size while increasing computing power.
While these stacked die packages have increased functional integration in ultra thin profiles, the lack of known good sub-assemblies in these stacked die packages necessitates the pre-testing of packaged three-dimensional configurations. As a result, stacking pre-tested packages together in a single configuration is emerging as an option. For example, these options include package-on-package (PoP) three-dimensional technology and package-in-package (PiP) three-dimensional technology. PoP is a three-dimensional package structure in which fully tested packages, such as, single die Fine Ball Grid Array (FBGA) or stacked die FBGA are stacked one on top of another single die or stacked die FBGA. PiP technology employs stacking a tested internal stacking module on top of a base assembly package to form a single chip scale package.
PoP and PiP three-dimensional technology is becoming popular due to their KGD aspect. However, one of the major disadvantages of this technology is that for the bottom package, only the area directly around the dies are molded, leaving the outer perimeter regions of the substrate exposed. These exposed outer perimeter substrate regions, which contain electrical connection sites and no molding compound, are subject to severe warpage after ball mount and reflow. The warpage of the bottom substrate arises due to the differences in thermal expansion between the semiconductor chip, the substrate, the solder balls and the molding compound. Most notably, after deposition of the molding compound, the over-contraction of the molding compound during cooling causes the substrate to warp.
Substrate warpage becomes an issue in stacked package design because of failed interconnects between a top and bottom package. Since substrate warpage causes the solder balls to be located out of plane, they make a poor electrical connection or fail to make an electrical connection at all with the target substrate. Such inconsistencies in stacked package configurations cause unacceptable package yields and unacceptable device failures upon integration into consumer products. Needless to say, such inconsistencies can also increase production costs.
Attempts have been made to combat the warpage of substrates. For instance, reinforcement layers have been affixed to the surfaces of substrates to provide structural support. Unfortunately, such measures require extra processing steps, which can increase the cost of production.
Other attempts to combat substrate warpage have incorporated a flexible adhesive agent between adjacent substrates or packages. Unfortunately the adhesive agents add bulk to the overall chip design, and consequently, are contrary to the goals of semiconductor manufacturing of reducing package dimensions.
Finally, additional attempts at controlling substrate warpage include depositing an encapsulation layer and then lasing through the encapsulation layer to uncover the electrical circuitry. Regrettably such attempts contend with damage caused by the laser and also require additional manufacturing steps, which increase the cost of production.
Thus, a need still remains for stacked package configurations that exhibit solid and consistent electrical connections between adjacent packages. In view of the ever-increasing need to save costs and improve efficiencies, it is more and more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.